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Formal Verification Architect

November 17, 2025

Job Description:

Verify microarchitecture using industry standard Formal Verification tools and technologies
Define the Formal Verification scope and deploy the right strategy to prove correctness
Create comprehensive formal verification test plans and ensure a high-quality design on schedule
Work with vendors to resolve design and tool problems

Requirements:

Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 9 years relevant experience or schoolwork
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 6 years relevant experience or schoolwork
PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field with 4 years relevant experience or schoolwork
Experience in RTL languages like System Verilog or VHDL
Experience in assertion languages like SVA
Experience in formal verification

Benefits:

competitive pay
stock
bonuses
health programs
retirement plans
vacation

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